Samsung showcases chip 3D architecture strategy at SEMICON Taiwan

Samsung Electronics on Tuesday showcased its 3D architecture strategy to break through current limitations in memory chip manufacturing during SEMICON Taiwan 2026, an international exhibition covering semiconductor design, manufacturing, testing and packaging. According to the company, Samsung Electronics Device Solutions Vice President Choi Jang-seok delivered a keynote speech at the Memory Executive Summit, a preview event for SEMICON Taiwan 2026, which will begin its three-day run on Wednesday. During his speech, Choi said Samsung is pushing the limits of memory technology with its “CUBE” strategy, which applies 3D technologies across memory chip manufacturing processes to improve capacity, utilization, bandwidth and efficiency. In memory chips, 3D architecture stacks chip dies or other components vertically to shorten the physical distance data must travel, increase data pathways and improve energy efficiency. It is called 3D architecture because chips or memory dies are stacked vertically instead of being placed side by side on a two-dimensional plane. High-bandwidth memory (HBM